After several experiments with jumpers and flash programming retries, Xilinx iMPACT failed to program the XCF04S device with verify errors... But when I fired Adept ExPort,
the flashing process was sucessful. Looks like the new iMPACT (v.9.2.04i) is not the way to go... So, we have programmed the platform flash, but still the board is unable to boot from it. After tinkering again with some ISE WebPACK options, I found the problem.
Usually, when building the project we upload the bitstream via the JTAG interface, so the bitstream is configured to be clocked with "JTAG-clock". If we convert the bitstream to a PROM file like this
promgen -w -x xcf04s -p mcs -u 0 bitstream.bit
we get bitstream.mcs ready to be put into the platform flash device. But it won't boot from it whatever you do. The solution is to change the clock source for the bitstream using "Generate Programming File" -> "Properties" -> "Startup Options" and to set the property "FPGA Start-Up Clock" to "CCLK" value. This will ensure that when FPGA boots from its flash, data will be transferred using the on-board clock, not JTAG clock. So, we succeeded :)
Just as a reminder to everyone (including me), don't forget to set ON all jumpers on J8 (M0, M1, M2), and to set in "Default" position JP1 jumper, otherwise FPGA won't boot (again!).
If you made it through, the prize will be one green LED with label "DONE" ;)
I was afraid at the beginning that the Spartan 3 FPGA or platform flash were defective, but now I'm relaxed.
the flashing process was sucessful. Looks like the new iMPACT (v.9.2.04i) is not the way to go... So, we have programmed the platform flash, but still the board is unable to boot from it. After tinkering again with some ISE WebPACK options, I found the problem.
Usually, when building the project we upload the bitstream via the JTAG interface, so the bitstream is configured to be clocked with "JTAG-clock". If we convert the bitstream to a PROM file like this
promgen -w -x xcf04s -p mcs -u 0 bitstream.bit
we get bitstream.mcs ready to be put into the platform flash device. But it won't boot from it whatever you do. The solution is to change the clock source for the bitstream using "Generate Programming File" -> "Properties" -> "Startup Options" and to set the property "FPGA Start-Up Clock" to "CCLK" value. This will ensure that when FPGA boots from its flash, data will be transferred using the on-board clock, not JTAG clock. So, we succeeded :)
Just as a reminder to everyone (including me), don't forget to set ON all jumpers on J8 (M0, M1, M2), and to set in "Default" position JP1 jumper, otherwise FPGA won't boot (again!).
If you made it through, the prize will be one green LED with label "DONE" ;)
I was afraid at the beginning that the Spartan 3 FPGA or platform flash were defective, but now I'm relaxed.